Education: Master’s/Bachelor’s Degree in engineering from a reputed college.
Experience & Skills:
2 – 5 years of experience in RTL design, functional verification, and SOC-level verification. In-depth knowledge of Verilog/System Verilog is required.
Proficiency with Verification methodologies like OVM or UVM and solid debugging skills is desired. Thorough knowledge of Digital timing and synthesis concepts is a must.
Good to have skills:
- Knowledge of MIPS/ARM processors and interfaces such as AHB, APB, and AXI.
- Experience with industry-standard synthesis and simulation tools is desired.
- Knowledge of FPGA systems and debugging the system on FPGA is desired.
- Post silicon debugging skills would be ideal.
Roles & Responsibilities:
- Accountable for specification, design, and verification of different peripherals, interconnects, network accelerators, signal processing accelerators, and SOC hardware IP.
- Work closely with firmware/physical design/algorithm and system engineers for complete closure of the block(both in ASIC and FPGA).
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